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Extra info for ACM transactions on design automation of electronic systems (April)
To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. org. 00 ACM Transactions on Design Automation of Electronic Systems, Vol. 10, No. 2, April 2005, Pages 229–257. 230 • I. Kadayif et al. 1. INTRODUCTION Power optimization has become as important a criterion as performance across a spectrum of computing devices. While the need for conserving battery energy on embedded devices is well understood [Catthoor et al.
A common technique, which we adopt here as well, is to first decompose the netlist into trees. Several ways of decomposing a netlist into trees are available. In this article, we first compute the logic depth of all primary outputs. We find the fan-in cone of the primary output with the largest logic depth and use that to define a tree rooted at the primary output. The leaf nodes of the tree are all primary inputs. Therefore, the evaluation time of the tree is set to be the given evaluation period Tev , and the dynamic programming-based approach described in the previous section is applied.
However, there are caches (L1 and L2) before going to the DRAM, and how these caches are looked ACM Transactions on Design Automation of Electronic Systems, Vol. 10, No. 2, April 2005. 234 • I. Kadayif et al. up can have an impact on iTLB performance and power. It should be noted that cache lookup requires an indexing part to determine the set under consideration, and a subsequent tag comparison for the blocks within the set. Either of these can be done with a virtual address or a physical address, leading to four possible combinations: virtually indexed, virtually tagged (VI-VT), virtually indexed, physically tagged (VI-PT), physically indexed, physically tagged (PI-PT), and physically indexed, virtually tagged (PI-VT).