Download Analog Circuit Design: High-speed Clock and Data Recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier PDF

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

Analog Circuit layout includes the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. each one half discusses a selected to-date subject on new and necessary layout principles within the region of analog circuit layout. every one half is gifted through six specialists in that box and cutting-edge details is shared and overviewed. This publication is quantity 17 during this profitable sequence of Analog Circuit layout.

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Additional resources for Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management

Sample text

If the divide value is stepped by a large value, the PLL will cycle slip many times before re-acquiring frequency lock, and thereby invalidate our modeling assumptions. Fortunately, a well designed fractional-N frequency synthesizer system can always be ramped in frequency slowly enough to avoid losing frequency lock, so that our modeling assumptions will be accurate for most practical cases. Otherwise, if an estimate of the nonlinear behavior exhibited during cycle slipping is desired, simulation tools such as described later in this chapter can be used.

Analog Circuit Design, 27-49. © 2003 Kluwer Academic Publishers. Printed in the Netherlands. 28 Dithering of the divide value by the modulator allows high frequency resolution to be achieved, but also has the negative side effect of introducing quantization noise that degrades the overall PLL noise performance [1]. It is highly desirable to be able to calculate and simulate the impact of this quantization noise, along with other noise sources in the PLL shown in Figure 2, on the overall PLL performance.

Perrott, “Fast and Accurate Behavioral Simulation of Fractional-N Synthesizers and other PLL/DLL Circuits”, Design Automation Conference (DAC), 2002, pp 498-503. S. H. Perrott, B. Setterberg, A. Grzegorek, W. 5 GHz Sigma-Delta Frequency Synthesizer with 5 microseconds Settling and 2 Mb/s Closed Loop Modulation”, International Solid-State Circuits Conference (ISSCC), 2000, pp 200201. Y. H. Perrott, “Fractional-N Frequency Synthesizer Design at the Transfer Function Level Based on a Direct Closed Loop Realization Algorithm”, DAC, 2003.

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