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Download Assessing Fault Model and Test Quality by Kenneth M. Butler PDF

By Kenneth M. Butler

For decades, the dominant fault version in automated attempt trend gen­ eration (ATPG) for electronic built-in circuits has been the stuck-at fault version. The static nature of stuck-at fault checking out compared to the super dynamic nature of built-in circuit (IC) know-how has prompted many to question even if stuck-at fault dependent trying out remains to be doable. makes an attempt at answering this query haven't been completely pleasurable as a result of an absence of actual quantification, statistical value, and/or excessive computational fee. during this monograph we introduce a technique to handle the ques­ tion in a fashion which circumvents the drawbacks of past methods. the strategy relies on symbolic Boolean sensible analyses utilizing Or­ dered Binary determination Diagrams (OBDDs). OBDDs were conjectured to be an enticing illustration shape for Boolean capabilities, even supposing instances ex­ ist for which their complexity is sure to develop exponentially with enter cardinality. periods of Boolean capabilities which make the most the efficiencies inherent in OBDDs to a really nice quantity are tested in bankruptcy 7. targeted equa­ tions giving their OBDD sizes are derived, while till very lately simply measurement bounds were to be had. those dimension equations recommend that instantly­ ahead functions of OBDDs to layout and attempt comparable difficulties won't end up as fruitful as was thought.

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This method also provides the capacity of comparing different test generation algorithms to see which has better non-target defect coverage statistics. There are some disadvantages to this approach, however. 2, many typical target faults are very detectable. Thus, there are often a very large number of possible test sets that guarantee very high or 100% coverage. The sample size of test sets would have to be very large in such cases to ensure a proper level of statistical significance. Moreover, the computational expense of repeated fault simulation for a large number of target fault test sets and non-target defects renders application of the method to large circuit sizes and circuit sets to be prohibitive.

By the definition of OBDDs appearing in [BRYA86], the value of any set of input conditions can be evaluated by tracing paths through the OBDD. Because no paths contain a vertex representing Xi, the value of f can always be determined regardless of the value of Xi· Thus, f is independent of Xi. This is in contradiction to our assumption that f is intrinsic, so the OBDD must contain at least one vertex representing Xi. This argument holds true ViE {I, 2, . . ,n} . 5. 5 over the symmetry diagram in this way, each of the remaining vertices represent unique residues and must therefore remain in the graphs.

X n ) which does not contain any vertices labeled Xi. By the definition of OBDDs appearing in [BRYA86], the value of any set of input conditions can be evaluated by tracing paths through the OBDD. Because no paths contain a vertex representing Xi, the value of f can always be determined regardless of the value of Xi· Thus, f is independent of Xi. This is in contradiction to our assumption that f is intrinsic, so the OBDD must contain at least one vertex representing Xi. This argument holds true ViE {I, 2, .

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